1. Field of the Invention
The present invention relates to an EL (electroluminescence) display device formed by a semiconductor element (an element using a semiconductor thin film) made on a substrate, and to an electronic apparatus having the EL display device as a display (display portion).
2. Description of the Related Art
Techniques of forming a TFT on a substrate have been greatly advancing in recent years, and development of applications to an active matrix type display device have been progressing. In particular, a TFT using a polysilicon film has a higher electric field effect mobility (also referred to as mobility) than a TFT which uses a conventional amorphous silicon film, and high speed operation is therefore possible.
Shown in FIG. 3 is a general pixel structure of an active matrix type EL display device. Reference numeral 301 in FIG. 3 denotes a TFT which functions as a switching element (hereafter referred to as a switching TFT), reference numeral 302 denotes a TFT which functions as an element (hereafter referred to as an electric current control element) for controlling electric current provided to an EL element 303, and 304 denotes a capacitor (storage capacitor). The switching TFT 301 is connected to a gate wiring 305 and to a source wiring (data wiring) 306. A drain of the electric current control TFT 302 is connected to the EL element 303, and a source of the electric current control TFT 302 is connected to an electric current supply wiring 307.
A gate of the switching TFT 301 opens when the gate wiring 305 is selected, a data signal of the source wiring 306 is stored in the capacitor 304, and a gate of the electric current control TFT 302 opens. After the gate of the switching TFT 301 closes, the gate of the electric current control TFT 302 remains open in accordance with the electric charges stored in the capacitor 304, and the EL element 303 emits light during that period. The amount of light emitted by the EL element 303 is changed by the amount of electric current.
In other words, the amount of electric current flowing in the electric current control TFT 302 is controlled by the data signal input from the source wiring 306 in an analog drive gradation display, and the amount of light emitted by the EL element thereby changes.
FIG. 4A is a graph showing the transistor characteristics of the electric current control TFT 302, and reference numeral 401 denotes an Id-Vg characteristic (also referred to as an Id-Vg curve). Id is a drain current, and Vg is a gate voltage here. The amount of electric current flowing with respect to an arbitrary gate voltage can be found with this graph.
A region of the Id-Vg characteristic shown by a dotted line 402 is normally used in driving the EL elements. An enlargement of the region enclosed by the region 402 is shown in FIG. 4B.
The shaded region in FIG. 4B is referred to as a subthreshold region. In practice, this indicates a region having a gate voltage in the neighborhood of the threshold voltage (Vth) or below, and the drain current changes exponentially with respect to changes in the gate voltage within this region. Electric current control is performed in accordance with the gate voltage by using this region.
The data signal input to the pixel when the switching TFT 301 in FIG. 3 is open is first stored in the capacitor 304, and then the signal becomes the gate voltage of the electric current control TFT 302, as is. The drain current is determined at this time by a one to one correspondence with respect to the gate voltage, in accordance with the Id-Vg characteristic shown in FIG. 4A. Namely, a predetermined electric current flows in the EL element 303 in correspondence with the data signal, and the EL element 303 emits light with the amount of light corresponding to the amount of current flow.
The amount of light emitted by the EL element is thus controlled by the input signal, and gradation display is performed by controlling the amount of light emitted. This method is referred to as analog gradation, and gradation display is performed by changing the amplitude of the signal.
However, the above analog gradation method has a disadvantage of being extremely weak with respect to dispersions in the TFT characteristics. For example, suppose that the Id-Vg characteristic is a switching TFT and differs from that of a switching TFT of an adjacent pixel displaying the same gradation (a case of an overall positive of negative shift).
In this case the drain current of each switching TFT differs on the order of the dispersion, and the gate voltages applied to the current control TFTs of each pixel therefore also differ. In other words, the electric current flowing differs for each of the EL elements, and as a result, the amount of light emitted also differs, and the same gradation display cannot be performed.
Further, even supposing that equal gate voltages are applied to the electric current control TFTs of each pixel, the same drain current cannot be output if there are variations in the Id-Vg characteristics of the electric current control TFTs. In addition, even if equal gate voltages are applied, the amount of electric current output differs greatly if even small deviations exist in the Id-Vg characteristics when using a region in which the drain current changes exponentially with respect to changes in the gate voltage, as is clear from FIG. 4A. The amount of light emitted by adjacent pixels will differ greatly as a result.
In practice, there is a multiplier effect between dispersions in both the switching TFTs and the electric current control TFTs, and this makes achieving the conditions more difficult. Thus the analog gradation method is extremely sensitive with respect to variations in the TFT characteristics, and this becomes an obstacle to multiple colorization of a conventional active matrix EL display device.
In consideration of the above problems, an object of the present invention is to provide an active matrix type EL display device capable of sharp, multi-gradation color display. In addition, an object of the present invention is to provide a high performance electrical apparatus furnished as a display portion of this type of active matrix EL display device.
The applicant of the present invention considers that in order to make a pixel structure which is not readily influenced by dispersions in TFT characteristics, a digital driver gradation method, in which an electric current control TFT is used as a simple electric current supply switching element, is better than a conventional analog driver gradation method of controlling the amount of light emitted by an EL element in accordance with electric current control.
It is considered that a time division method of gradation display (hereafter referred to as time division gradation) will be performed by a digital driver in the active matrix type EL display device.
In addition, a panel display can be made higher speed by dividing video lines and inputting a plurality of data at one time when inputting a video signal into a source driver circuit. Note that the video signal referred to here is a data signal input into the source driver circuit throughout this specification.
FIGS. 5A to 5F show the overall driver timing of the write-in period and the display period when performing time division gradation display. A case of performing 64 gradation display in accordance with a 6 bit digital driver method is explained here. Note that the write-in period is the time required for a signal to be written into all pixels structuring one frame, and that the display period is the period in which the pixels perform display of the write-in signal.
An EL driver power supply is cut (all pixels turn off) during the write-in period, and the EL elements within the pixels are in a state of no applied voltage. Further, the EL driver power supply is input during the display period, placing the EL elements within the pixels in a state of having an applied voltage. At this point the pixels turn on when the data signal for turning on the pixels is input.
A period in which an image is completely displayed in an image region is referred to as one frame period. The oscillation frequency of a normal EL display is 60 Hz, and 60 frames exist during one second, as shown in FIG. 5A. For example, when performing 6 bit digital gradation display (64 gradations) in a fourth frame, if one frame is divided into 16 partitions and the ratio of the write-in period to the display period is determined as 6:10, then writing in can be performed 6 times (≈6.24 msec) during the write-in period, as shown in FIG. 5B. Note that the six write-ins 1 to 6 are performed in order from 1 to 6. Further, the display periods corresponding to the write-in periods (from write-in 1 to write-in 6) are set as displays 1 to 6, respectively.
Furthermore, the display periods are set so that display 1:display 2:display 3:display 4:display 5:display 6=1:1/2:1/4:1/8:1/16:1/32.
FIG. 5C shows a state in which each display period has the above stated ratios with respect to the write-ins when performing 6 write-ins (write-in 1 to write-in 6) during one frame. The values shown in the lower portion of FIG. 5C show the relationship between the lengths of the write-in periods and the display periods.
Specifically, the display period (display 1) in the write-in 1 shows a value of 320 when the write-in period is 63. In addition, the display 2 has a display period of 160, the display 3 has a display period of 80, the display 4 has a display period of 40, the display 5 has a display period of 20, and the display 6 has a display period of 10 with respect to each of the write-in periods having a value of 63.
One write-in period (write-in) and one display period (display) together are referred to as one field. Namely, six fields exist in FIG. 5C, all having constant write-in periods and differing display periods. In order to complete one frame here, the first field displayed at the beginning is referred to as a field 1 (F1), and the fields displayed subsequently below are referred to as fields 2 to 6 (F2 to F6), in order.
Note that the order of appearance of the fields 1 to 6 may be arbitrary. By combining the display periods, a desired gradation display, from among the 64 gradations, can be performed.
Further, in practice the timing is a combination of the six dispersed fields having different display periods, as shown in FIG. 5D.
If predetermined pixels are turned on during the period of the display 1 in FIG. 5D, then the write-in 5 is entered and after the data signal is input to all of the pixels, the display 5 is entered. Next, the display 4 is entered after the data signal is input to all of the pixels in the write-in 4. Predetermined pixels are also similarly turned on by the respective fields in the write-in 2, the write-in 3, and the write-in 6.
FIG. 5E shows the period during which the data, with which a certain gate line is selected by the data signal input from a gate circuit in the field 5 from among the six fields shown in FIG. 5D, is written (the write-in 5). FIG. 5E also shows the display period (the display 5) in which the signal from a source line input from a source line to the selected gate line and the pixels perform display.
FIGS. 5A to 5E are based on a VGA (640xc3x97480) panel display, and therefore there are 480 gate wirings and in addition, a period for selecting all of the gate lines, including a certain number of dummies, is a write-in period of FIG. 5E.
The signal input from the source lines in the write-in period is referred to as dot data. The dot data input from a source driver circuit during one gate selection period is sampled during a period shown in FIG. 5F. This shows the gate data selected during the write-in period being written in, at the same time as showing the signal input from the source lines being written in. Note that the period for the data to be sampled at one time is 40 nsec.
Note also that the dot data input from the source driver circuit is input at the same time at 16 bits per 40 nsec as shown in FIG. 5F.
In addition, the dot data selected in one gate selection period is stored in a latch 1 (6001) within the source driver circuit shown in FIG. 6 until all of the data sampling is completed. After all sampling is finished, latch data is input from a latch line 6003, and all of the data is moved at once to a latch 2 (6002). Note that a shift register 6004 selects a video signal input from a video line 6006 in accordance with a clock pulse from a clock line 6005.
In addition to the sampling period, a line data latch period formed in FIG. 5F is a period in which a latch signal is input when moving the data from the latch 1 (6001) to the latch 2 (6002), and in which the data is moved.
A pixel structure of an active matrix type EL display device of the present invention is shown in FIG. 7. Reference numeral 701 in FIG. 7 denotes a TFT which functions as a switching element (hereafter referred to as a switching TFT or a pixel switch TFT), reference numeral 702 denotes a TFT (hereafter referred to as an electric current control TFT or an EL driver TFT) which functions as an element (electric current control element) for controlling the electric current supplied to an EL element 703, and reference numeral 704 denotes a capacitor (also referred to as a storage capacitor or a supplementary capacitor). The switching TFT 701 is connected to a gate line 705 and a source line (data line) 706. Further, a drain of the electric current control TFT 702 is connected to the EL element 703, and a source of the electric current control TFT 702 is connected to an electric current supply line (also referred to as an EL driver power supply line) 707.
A gate of the switching TFT 701 opens when the gate line 705 is selected, the data signal from the source line 706 is stored in capacitor 704, and a gate of the electric current control TFT 702 opens. Then, after the gate of the switching TFT 701 closes, the gate of the electric current control TFT 702 remains open in accordance with the electric charge stored in the capacitor 704, and the EL element 703 emits light during that time. The amount of light emitted by the EL element 703 changes by the amount of electric current flowing.
In other words, the gate of the electric current control TFT 702 opens or closes in accordance with the data signal input from the source line 706 in the digital drive gradation display, and if the EL driver power supply is on, electric current flows and the EL element emits light.
The function of the electric current control TFT of the pixel is to control whether or not the corresponding pixel is turned on (display) or is turned off (non-display) during the display period. The switching between the display period and the write-in period is performed by a power source external to the right panel, through an FPC terminal.
Further, an electric power supply attached externally to the panel (reference numeral 709 in FIG. 7) achieves a switching function for switching between the write-in period and the display period. In the write-in period the electric power supply is in an off state (a state in which there is no applied voltage), and the data signal is input to each of the pixels.
After the data in input to all of the pixels and the write-in period is complete, the electric power supply (reference numeral 709 in FIG. 7) in turned on and display is performed all at once. This period becomes the display period. The period in which the EL elements emit light and the pixels are turned on is any of the periods from the display 1 to the display 6 from among the six fields.
After the six fields have appeared, one frame becomes complete. The gradation of a pixel is controlled by adding up the display periods at this point. For example, when the display 1 and the display 2 are selected, a brightness of 76% can be expressed out of a full brightness of 100%, and when the display 3 and the display 5 are selected, a brightness of 16% can be expressed.
Note that although a case of 64 gradations is explained above, it is also possible to perform other gradation displays.
Assuming that N bit (where N is an integer greater than or equal to 2) gradation display is performed (2n gradations), then first one frame is divided into N fields (F1, F2, F3, . . ., F(nxe2x88x921), F(n)) corresponding to the N bit gradations. The number of divisions of one frame increases with increasing gradations, and the driver circuit must by driven at a high frequency.
In addition, each of the N fields is separated into write-in periods (Ta) and display periods (Ts).
The display periods (note that display periods corresponding to F1, F2, F3, . . ., F(nxe2x88x921), F(n) are expressed as Ts1, Ts2, Ts3, . . ., Ts(nxe2x88x921), Ts(n), respectively) of the N fields are processed so as to become Ts1:Ts2:Ts3: . . . :Ts(nxe2x88x921) Ts(n)=20:2xe2x88x921:2xe2x88x922: . . . 2xe2x88x92(nxe2x88x922):2xe2x88x92(nxe2x88x921).
In this state, pixels are selected in order in one arbitrary field (strictly speaking, the switching TFT of each pixel is selected), and the predetermined gate voltage (corresponding to the data signal) is applied to the gate electrodes of the electric current controlling TFTs. The EL elements of pixels to which a data signal, which makes the electric current control TFTs have a continuity state, is input to turn on the pixels for the display periods apportioned to those fields when the electric power supply is input after the write-in period is complete.
This operation is repeated in all the N fields, and gradation of each pixel is controlled in one frame by adding the display periods. Therefore in focusing on one arbitrary pixel, the gradation of one pixel can be controlled on the basis of for how long a period the pixel was lighted in each field (how many display periods have passed).
Thus the most important aspect of the preset invention is that the digital driver time dividing gradation method is used in the active matrix type EL display device. It becomes possible to perform gradation display without any influence from the TFT characteristics, a problem in analog driver gradation display, by using this time division gradation driver.